Cadence入门进阶：inverter版图寄生参数提取与后仿

写在前面的话：这篇还在讲Cadence的入门。请各位牛人们不要浪费时间看这篇了哈！

接着上次的课程介绍：这次讲讲一个inverter 的寄生参数提取和后仿。

3.6 Parasitic Extraction - PEX

This PEX tool will extract all the parasitic (resistance and capacitance) of the layout netlist. After which, we will run a post-layout simulation based on the extracted parasitic netlist. This will give a better representation of the simulation results. Let's begin once again.

1. In the Layout window, go to Calibre and click on Run PEX. The window below will pop-up. Press OK.

2. Click on Rules, under PEX Rules File, type: /net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/xrc.rf

This is as shown below.

3. Click on Outputs, change the Format to CALIBREVIEW. Ensure that the Extraction Type: R+C+CC. Click on PEX Options, under Netlist Tab, make sure you fill up GND in the field of the Ground node name. （抽取：寄生电阻R，到sub的寄生电容C，和device以及金属线之间的寄生电容CC）

4. Under LVS Options Tab, make sure you fill up VDD and GND in the field of power and ground nets respectively. （因为抽取寄生的时候会再做一遍LVS）

5. Under Connect Tab, make sure you highlight on the Don't connect nets by name. After which, press the Run PEX button.

6. A window will appear. In the Cellmap File, type: /net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/Calibre_XRC_amis500cxakxx.cellmap

Click on Schematic as shown by arrow below. Under Open Calibre Cellview, click Read-Mode as shown by arrow below. Press OK.

7. The Calibre Info dialog box will appear and press Close.

8. At the same time, there is a new window which shows the extracted parasitic (resistance and capacitance) . It is illustrated below.

9. In the Library Manager, go to File, New and Cellview. Type in config under View Name and change to Hierarchy-Editor. It is illustrated below. Press OK.

10. Another New Configuration window appears, type in schematic under View. It is shown below. Press Use Template.

11. Another dialog box pop up, ensure that it is spectre under Name. Press OK.

12. Press the Save button shown by rectangle below. Exit this window.

13. Hello. I know that you are very exhausted now. Hang on! We are reaching the finishing line soon. Maybe you can take a break and have a drink now. I am alright with it. Now, go back to your schematic window.

14. Go to Design, Create Cell View and then From Cell View. The below window pops up. press OK. This step is to create a symbol for your schematic.

This is a MUST for post-layout simulation (PLS).

15. Another window - Symbol Generation Options appears. Fill up the details as shown below. Press OK.

16. The symbol window will pop up. Press Shift and x to save it.

17. In the Library Manager, go to File, New and Cellview. Create a new Cell Name as Lab_3_inverter_test_bench. Type in schematic under View Name and change to Composer-Schematic. It is as shown below. Press OK.

This is a MUST to create another Cell Name in order to run Post-Layout Simulation (PLS).

18. The new schematic window opens up. Press i and look for the symbol that you had created in Lab_3_inverter. Add that symbol into the schematic and it will look like the one shown below. Press Shift & E to descend into symbol. Press Control & E to descend out of the symbol.

19. Wire up the connections as shown below. Press Shift and x together to save it.

21. Another New Configuration window appears, type in schematic under View. It is shown below. Press Use Template.

22. Another dialog box pop up, ensure it is spectre under Name. It is shown below. Press OK.

23. In the window shown below, right click on the highlighted line shown by w below and change the View Found to calibre.Press the Save button as indicated by the rectangle below. Exit this window.

24. Go to the test bench schematic window, we are READY for Post-Layout Simulation (PLS). I have added a dummy capacitor for simulation purpose. I can feel your happiness now. Congratulations! I admired your determination and perseverance. Excellent Work!

3.7 Post-Layout Simulation - PLS

1. Now, you can carry on with your simulation as usual. Go to Tools and then Analog Environment. Your simulated results would be your post-layout simulation results which take into account of the parasitic resistance and capacitance.

Additional Hints:

1. Now, you highlight the symbol, press Shift and e together. Press OK when a descend window pops up. You will see the presence of parasitic resistor and capacitor below the NMOS and PMOS transistors.

2. For every login, you open up Library Manager, go to test bench cell view and opened the config view NOT the schematic view. After which, continue your post-layout simulation.

Now, we had finally completed the whole cycle!

Next, comes the BIGGESTCHALLENGE!

The next exercise is an INDIVIDUALASSIGNMENT. It is tedious but fun and enjoyable. Please be prepared that you would need to spend at least one month to complete the whole assignment. You will spend most of your time working on the circuit simulation to satisfy all the specification requirements. You need to have lots of patience and determination during the entire circuit simulation.

Whenever necessary or possible, take a break ....No worries, I will try my ultimate best to assist you whenever possible or impossible. Let's continue the journey for your individual assignment.

Rule of Thumb: Perseverance & Sheer Determination are the key to success!

———————————————————————————————————————

原创声明：本文为原创，未经许可，严禁转载。如需转载，请联系作者。

微信公众号：analogIC_gossip