Cadence逆变器版图验证入门

Design Rule Check - DRC

Wikipedia：Design rule checking or check(s) (DRC) is the area of electronic design automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules.

也就是说，foundry告诉你，你画出的版图只有满足了这个文件的要求，它才能保证给你正确的做出来（请注意：精度不一定可靠，但是理论上来说可以做。）比如一个180nm的CMOS工艺，你的transistor的length要大于180nm，你所用的金属连接线之间的间距不能小于某个值，你的金属线线宽也必须大于某个值。

所以，为了形成一个好习惯，我建议你开始画版图之前，读一下foundry的文档，大致浏览一下各种最小线宽之类的要求。

当然了，线宽除了foundry的要求，跟它上面可能会经过的最大电流也有关系。比如一个很经典的值：1um的金属线，最大可以承担的电流是1mA。而且为了保险起见，我常常会用3~5倍或者更大的线宽。不过，更大的线宽虽然可以有效的减小金属线的导通电阻，却也会使得寄生电容变大。如何折衷选择，还是看具体的实际要求。

1. In the Layoutwindow, go to Calibre and press Run DRC.

Some students may not have the Calibre option in the layout window. If that is the case, kindly follow the instructions below:

· Open Terminal

· Type cp/net/cics/inux01/usr1/.cdsinit .

· Close the existing terminal & Cadence application

· Login to Cadence again.

The Calibre Interactive window will appear as shown below. Press OK.

2. Click on Rules, under DRC Rules File, type: /net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/drc.rf

（加入你所使用的工艺库的drc文档）

Take note: The DRC Run Directory must be valid accordingly to individual directory. Check with your teaching assistant now if you face any problems.

3. Click on the Run DRC button in Calibre Interactive window. A few different windows will pop up. Now, there are errors indicated in RED. Why?

Please do not panic. The results are OK. The errors suggested are referring to the density of metal 1, 2 and 3 being < 30% of the whole area. Furthermore, the net area of the layout are too small as well. No worries. These errors are trivial and have NO impact on your post-layout simulation done later.

So is this the end of the exercise?

No, not at all.

We still have to perform the next check which is Layout Vs Schematic Check (LVS). This LVS tool will extract the schematic netlist and compare with the layout netlist. This is sometimes referred to as layout parameter extraction.

LVS就是用来对比你的schematic和你的layout是不是一致的。虽然大部分时候你都觉得我的连线肯定是正确的，但是……你是人嘛！人肯定有可能出错的。不过，几十年前，还没有LVS的时代，据说真的是靠人工检查的……不过那会电路的device远远少于现在啊！

Please do not CONFUSE this with Layout Parasitic Extraction. They are DIFFERENT.

Layout Vs Schematic - LVS

1. In the Schematicwindow, press p. The Add Pin window will appear as shown below. Under Pin Names, type Vin. Make sure that the direction is input.

Take note: We have to add pins to our schematic before we can run LVS successfully.

2. Continue to add the other 3 pins: VDD, GND and Vout. Your schematic will resemble the one shown below. Kindly let me know if you encounter any difficulties.

Take note: The direction for VDD and GND is inputoutput but Vout will be output.

WAIT! What must you DO after making valid changes to your schematic?

Save your schematic by pressing............I think you should know already. I am very proud of you. Let's continue.

3. In the Layout window, go to Calibre, Setup and then Netlist Export. The window will appear as shown below. For the field under Include File, type:

/net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/box.cdl

Press OK.

4. In the Layout window, go to Create and press Pin. The Create Symbolic Pin window will appear as shown below. Type in VDD under Terminal Names. Click on Display Pin Name Option. The Pin Name Display window appears. Make sure that it is pinned to the correct metal 1 layer as shown below.

5. Continue to add the other 3 pins: Vin, GND and Vout. Your schematic will resemble the one shown below. Kindly let me know if you encounter any problems.

You MUST pin it correctly otherwise your LVS check will FAIL!

（大家别真的认为inverter应该这样画……这样太浪费面积了，只是拿来讲讲流程所用，实际上device放得很密，金属线也没这么铺张浪费……而且最重要的是：如果你有standard cell的library，inverter的layout早已经被人做好了…………^_^）

6. Looks like we are now ready for LVS. In the layout window, go to Calibre and click on Run LVS. Go to Setup and click on the square box beside LVS Options. The window below will pop-up.

7. Click on Rules, under LVS Rules File, type: /net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/lvs.rf

8. Click on LVS Options, under Supply Tab, make sure that it is the same as the one shown below.

9. Under Gates Tab, make sure that it reassembles the one shown below.

10. Under Inputs, go to Netlist Tab, click on the square box beside Export from schematic window. Click Run LVS button.

11. A few different windows will pop-up as shown below. I am sure you will see the smiling face. Looks good! No errors found. I am delighted with your extraordinary achievements. You have improved a lot over the past few lab exercises.

Yes, it is the end. Wait.

Not just yet!

But I assure you that we are inching towards the finishing line soon. Be patient. You may wish to take a short break before continuing the next part. No worries, be HAPPY. I am perfectly OK with that.

总算绿了！恭喜恭喜！

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