Verilog四位计数器设计与仿真波形分析

先上一段计数器的verilog代码：

/*4位计数器这例子非常好的表达了一个概念就是同步复位的概念。这个概念非常重要，在XILINX的器件所有硬核都使用同步复位。如果使用异步复位需要多耗费资源。接着说计数器，计数器必须有时钟，如果要能进入到初始值，必须有复位输入。和一个计数器的输出。该4位计数器，三个选项全部具备。在时钟上升沿，如果复位信号有效，则复位为0,如果复位信号无效，则计数器需要加一。另外让大家思考下，如果是计数器的最大值是 13怎么办？低电平复位时钟上升沿计数 */ module count4(out,reset,clk); output[3:0] out; input reset,clk; reg[3:0] out; always @(posedge clk) begin if (reset) out<=0; //同步复位 else out<=out+1'b1; //计数 end endmodule1.

再附一首testbeach：

/* File Name : ctr_tb.v Description : The testbench of the ctr_4.v Written By : LiMing Data : 2011/04/19 16:13 modefied : Period = 4ns */ `timescale 1ns/1ns module test; /*Make a reset that pulses once.*/ reg reset = 0; initial begin #2 reset = 1; //reset #3 reset = 0; //start count #24 reset = 1; //reset #2 reset = 0; //start count #48 reset = 1; //reset #1 reset = 0; //start count #60 reset = 1; //reset #3 reset = 0; //start count #100 $stop; end /*Make a regular pulsing closk*/ parameter clk_period = 4; reg clk; initial clk = 0; always #(clk_period/2) clk = ~clk; wire[3:0] out; count4 ctr(out,reset,clk); initial $monitor("At time %t, value = %h (%0d)",$time, out, out); initial begin $dumpfile("test.lxt"); $dumpvars(0,test); end endmodule1.

再再附批处理文件：

ECHO OFF ECHO ********************************* ECHO * Batch file ECHO ********************************* ECHO * ECHO ON iverilog -o test ctr_4.v ctr_tb.v vvp -n test -lxt2 gtkwave test.lxt1.

运行结果：

G:\Verilog HDL\examples\Verilog135\02_4bitctr>go.bat G:\Verilog HDL\examples\Verilog135\02_4bitctr>ECHO OFF ********************************* * Batch file ********************************* * G:\Verilog HDL\examples\Verilog135\02_4bitctr>iverilog -o test ctr_4.v ctr_tb.v G:\Verilog HDL\examples\Verilog135\02_4bitctr>vvp -n test -lxt2 LXT2 info: dumpfile test.lxt opened for output. At time 0, value = x (x) At time 2, value = 0 (0) At time 6, value = 1 (1) At time 10, value = 2 (2) At time 14, value = 3 (3) At time 18, value = 4 (4) At time 22, value = 5 (5) At time 26, value = 6 (6) At time 30, value = 0 (0) At time 34, value = 1 (1) At time 38, value = 2 (2) At time 42, value = 3 (3) At time 46, value = 4 (4) At time 50, value = 5 (5) At time 54, value = 6 (6) At time 58, value = 7 (7) At time 62, value = 8 (8) At time 66, value = 9 (9) At time 70, value = a (10) At time 74, value = b (11) At time 78, value = c (12) At time 82, value = d (13) At time 86, value = e (14) At time 90, value = f (15) At time 94, value = 0 (0) At time 98, value = 1 (1) At time 102, value = 2 (2) At time 106, value = 3 (3) At time 110, value = 4 (4) At time 114, value = 5 (5) At time 118, value = 6 (6) At time 122, value = 7 (7) At time 126, value = 8 (8) At time 130, value = 9 (9) At time 134, value = a (10) At time 138, value = b (11) At time 142, value = 0 (0) At time 146, value = 1 (1) At time 150, value = 2 (2) At time 154, value = 3 (3) At time 158, value = 4 (4) At time 162, value = 5 (5) At time 166, value = 6 (6) At time 170, value = 7 (7) At time 174, value = 8 (8) At time 178, value = 9 (9) At time 182, value = a (10) At time 186, value = b (11) At time 190, value = c (12) At time 194, value = d (13) At time 198, value = e (14) At time 202, value = f (15) At time 206, value = 0 (0) At time 210, value = 1 (1) At time 214, value = 2 (2) At time 218, value = 3 (3) At time 222, value = 4 (4) At time 226, value = 5 (5) At time 230, value = 6 (6) At time 234, value = 7 (7) At time 238, value = 8 (8) At time 242, value = 9 (9) G:\Verilog HDL\examples\Verilog135\02_4bitctr>gtkwave test.lxt1.

GTKWave的波形图：

全局 verilog之四位计数器（编译仿真查看波形）_批处理文件